The invention relates to a method of manufacturing an integrated semiconductor device on a substrate, comprising steps for forming at least two field effect transistors, both of the buried-channel type, with different pinch-off voltages.
Among the field effect transistors having different pinch-off voltages there are the enhancement-type transistor and the depletion-type transistor.
An enhancement-type transistor is understood to be a transistor which is blocked when there is no gate-source voltage (also called normally-OFF or N-OFF).
A depletion-type transistor is understood to be a transistor which is conducting when there is no gate-source voltage (also called normally-ON or N-ON).
The enhancement-type transistor has a pinch-off voltage which is more positive than that of the depletion-type transistor.
For simplicity's sake, the depletion-type transistor will be designated with D and the enhancement-type transistor with E hereinafter. These transistors are of different structure, i.e. the thickness of the active layer on which the gate contact is realised is different for each of them. This thickness is smaller for the enhancement-type transistor than for the depletion-type transistor.
In this manufacturing process, the invention relates exclusively to the case of semiconductor devices comprising transistors which have buried channels for realising the two types D and E. In that case, the active layer which supports the gate contact is buried below this gate contact, the gate contact thus being disposed in the recess so as to control more exactly the thickness of the active layer which governs the operation of the transistor.
The invention applies in particular to the realisation of integrated semiconductor devices including high electron mobility transistors (HEMT) of which the two types D and E are present on one and the same semiconductor substrate and are to be manufactured in the course of the same process.
The invention finds its application, for example, in the manufacture of semiconductor devices including an integrated circuit in which an amplifier stage comprises a type E transistor in the inverting mode with a type D transistor as the current source.
The invention finds its application in particular in the realisation of large scale integrated devices (LSI) or very large scale integrated devices (VLSI).
A manufacturing process for a semiconductor device, comprising steps for manufacturing two types of high electron mobility transistors on one and the same substrate is known from prior-art U.S. Pat. No. 5,023,675 of 11 Jun. 1991 (Tomoroni Ishikawa-FUJITSU Limited). This document describes a process for realising two types of transistors, the enhancement and depletion type, on one substrate. According to this known process, first a structure of active layers of semiconductor materials is realised. With reference to FIGS. 5 and 6 of the cited document, this stack comprises on a substrate 21 of semi-insulating InP a first layer 22 of InGaAs and a second layer 23 of InAlAs, constituting a heterojunction for the formation of a bidimensional electron gas at the interface. On this stack of active layers, a cap layer 24 is present, formed by three sub-layers: a lower layer 24a of n-type doped GaAsSb, an intermediate layer 24b of n-type doped InAlAs, and an upper layer 24c of n-type doped GaAsSb.
The intermediate layer 24b is provided as an etching stopper layer within the cap layer 24. Its thickness will be of the order of 2 to 3 nm.
This process further comprises steps for realising the two types of transistors, enhancement and depletion, each having a buried channel. To achieve the difference between these two types, the depth of the buried channel is different for each, from which it follows that the active layer arranged between the bottom of the buried channel where the Schottky gate contact will be and the interface where the bidimensional gas will be formed has a different depth, thus facilitating the operation in the depletion mode or in the enhancement mode, as applicable, of each of these transistors.
These steps comprise first the deposition of a dielectric layer 25 (SiO.sub.2) with openings for realising ohmic source and drain contacts. This dielectric layer 25 is retained throughout the process.
Subsequently, a photoresist layer 27 is deposited as a mask in which the gate opening 27a of the enhancement-type transistor is formed.
The process then continues with etching steps for starting the manufacture of the enhancement-type transistor:
a first etching step of the dielectric layer 25 through the gate opening 27a, PA1 a second etching step of the cap layer 24c down to the stopper layer 24b through selective RIE of the layer 24c without In (indium) through the gate opening 27a. This selective RIE stops at the layer 24b because the latter contains In (indium). The ratio between the RIE rate in the cap layer 24c without In and the RIE rate in the stopper layer 24b with In is 50, when a mixture of CCl.sub.2 F.sub.2 and He (helium) is used, PA1 a third selective etching step in the stopper layer 24b of InAlAs by wet etching in H.sub.2 SO.sub.4, H.sub.2 O.sub.2, H.sub.2 O. PA1 formation of the gate opening 27b in the photoresist masking layer, PA1 a second etching step of the dielectric layer 25 through the gate opening 27b, PA1 a second selective etching step of the cap layer 24c down to the stopper layer 24b through the gate opening 27b, which second etching step is similar to the second selective etching step already carried out for realising the enhancement-type transistor. PA1 a selective etching step of the lower cap layer 24a through the gate opening 27a by the same selective RIE means as in the second manufacturing step of each of the two transistors: i.e. in this process the selective RIE of the upper cap layer 24c of the depletion-type transistor is carried out substantially simultaneously with the selective RIE of the lower cap layer 24a of the enhancement-type transistor. PA1 a third selective etching step of the stopper layer 24b of InAlAs similar to the third selective etching step of the enhancement-type transistor previously realised. PA1 the enhancement-type transistor has a buried channel whose etching was stopped the moment the upper surface of the active layer 23 was exposed, PA1 the depletion-type transistor has a buried channel whose etching was stopped the moment the upper surface of the lower cap layer 24a was exposed. PA1 the realization of a stack of layers on a substrate, among which at least: PA1 a first selective etching step with a first etching compound comprising fluorine carried out in the cap layer through the gate openings of the two transistors until a stopper layer of aluminium fluoride is formed at the upper surface of the active layer, after which said stopper layer is eliminated, and the region of the first transistor is covered with a material which can be eliminated without deterioration of the masking layer previously deposited, PA1 a second non-selective etching step carried out in the active layer through the gate opening down to an intermediate level of the gate recess of the second transistor E, to a depth equal to the difference in depth between the gate recesses of the two transistors, followed by removal of the covering material, PA1 a third non-selective etching process carried out in the active layer simultaneously through the two gate openings of the two transistors down to the bottom level of the gate recess of the first transistor. PA1 it is formed automatically during said etching step in a reproducible position, which is the upper surface of the active layer, and indeed over the entire surface area of the substrate being treated, PA1 it stops automatically this ongoing etching step at this level, which serves as a reproducible reference over the entire surface of the substrate under treatment, PA1 it is formed to a thickness which is sufficient for stopping the ongoing etching step, PA1 it is formed to a thickness which is sufficiently small for being easily removed without prolonging the process or disturbing surfaces already formed, more particularly a thickness approximately 10 times smaller than the stopper layer present in the structure according to the present art.
The process is now temporarily stopped when the upper surface of the lower cap layer 24a is exposed as far as the realisation of the enhancement-type transistor is concerned; now the steps for realising the depletion-type transistor are started, comprising:
During this second selective etching step for the depletion-type transistor, the making of the enhancement-type transistor is resumed as follows:
The manufacture of the depletion-type transistor is continued with:
As a result, at the end of these selective etching steps:
This known process has disadvantages and renders it impossible to solve certain problems.
First, it has the disadvantage that it comprises twice two selective etching steps, which means that the designer of integrated circuits is not free to choose the semiconductor materials and etching agents.
It is an object of the present invention to provide a simpler process.
Furthermore, it has the disadvantage that the transistors obtained by this method are not really of the buried-channel type because only the cap layer is etched to a greater or lesser extent in dependence on the type of transistor. This cap layer is not the active layer; it simply serves to improve the ohmic source and drain contacts and to space apart the active layer from mechanical and electrical disturbances caused by the formation of the ohmic contact alloy. One of the transistors retains a portion 24a of the cap layer in its structure. The other transistor has its Schottky gate contact deposited directly on the upper surface of the active layer 23. Accordingly, neither of the transistor types benefits from the performance improvements following from the buried channel technology, which technology permits of a much more exact adjustment of the pinch-off voltages of the transistors.